Instructor:
Roger Traylor
Office: 238 ECE Bldg.
E-mail:traylor@ece.orst.edu
Office Hours: Tu, Th 3:00 - 4:00 or by appointment
When and Where:
Tuesday, Thursday 8:00-9:20 AM; Kidder 364
TA:
John Mark Matson
E-mail: matson@ece.orst.edu
Office Hours: Mon 3:00 - 4:00 or by appointment (Batcheller 253)
John Mark's 474 Page
Text
"Application-Specific Integrated Circuits" Michael John Sebastian Smith, Addison Wesley 1997
Prerequisites
The stated prerequisites are ECE 375 and ECE323. In reality, proficiency with UNIX,
really good with digital logic design, especially state machines and data paths.
Having taken ECE471, ECE472 and/or ECE473 really helps.
Supplemental Text
If you want to really dig into VHDL, Another good book to have is either
"The Designers Guide to VHDL" or "The Students Guide to VHDL" by Peter Ashenden.
SPAM Assembler and Testbench Stuff
Spasm Manual
Spam Simulator Manual
TAS Requirements document
TAS VHDL code in tar foramt
Spam risc core specification v1.3 (pdf format)
RISC core testbench in tar format
SPAM risc_core vhdl files in tar foramt
Spam tools tarball
UART Specification version 1.1
UART Specification version 1.3
Doing gate level simulation
VHDL Notes pages 0 - 23
VHDL Notes pages 24 - 46
VHDL Notes pages 44 - 60
VHDL Notes pages 61 - 76
VHDL Notes pages 77 - 106
VHDL Notes pages 107 - 127
In General:
This class focuses on system-level design and implementation of Very Large Scale Integrated (VLSI)
devices, specifically, ASICs. The emphasis is on system-level as opposed to circuit level issues.
However, a good understanding of CMOS digital circuits is required.
In the design realm, solutions are not singular. There are often many correctly functioning implementations for a given set of requirements. In this class you will most likely have a first encounter an large, open-ended design problem. It may seem overwhelming at first, but you will catch on after a while.
I will be looking for significant class participation. In a class where we are designing, we can all learn more if ideas and questions "flow". So....get the most out of class; ask questions. If your grade is on the edge, class participation can make a difference.
The Project
The centerpiece of this class is a large design project. It will be executed as it would be in a industrial
setting. As such, timeliness, neatness, and clarity are important. The project is presented as a precise
written description of how the system should work. Your job is first to write a very complete specification
of a VLSI system (a chip) that will implement the system. The specification will include all block diagrams,
interfaces, state machines, and data paths.
Once the specification is completed, you will describe the system in VHDL. This system is then simulated and modified until correct behavior is observed. The VHDL design is then synthesized into gates. The gate level design is then regressed against the VHDL description and checked for proper behavior and timing. After this, timing information is back annotated and regression is done again.
When your design is complete, you will submit your final revised specification. You will also electronically submit all your VHDL code. I will recompile, and resimulate it against a set of published test vectors.
Project Administration
You will design the project within a three partner group. I will set up the assigned groups.
I want to make sure that each group has at least one person who has taken ECE471 or ECE472. This
will give your team a leg up in VHDL and/or processor architecture.
At the end of the project, I will have each person submit how much they felt they did on the project, and how much their team mates did. Hopefully, the two will correlate. :^)
You will work alone on lab projects and homework. However, sharing of design approaches, philosophy, block diagrams or coding ideas is strongly suggested. Working in groups on labs is approved. However, sharing detailed information such as block diagrams, state machine diagrams, or actual VHDL code is not approved and will meet with the strongest action that I can bring.
This class will probably consume a VERY LARGE portion of your time. Be prepared to spend many hours designing, debugging, and simulating your design. Start early, work hard, You can sleep after you graduate.
Lab:
Much of the work for this class will be done in front of a UNIX workstation using various CAD tools
and scripts. If you don't understand UNIX well, it is time to learn. You should be comfortable
with navigating directory structures and creating files without using folder icons and such silliness.
You should be proficient with a good editor such as vi or emacs. Using
pico or that horrible HP desktop editor will really slow you down in writing code.
Students who register early for ECE474/574 are automatically added to the class mail list. You may not be on the list at first if you register late. You should be added within a day or so. The name of the class list for ECE474/574 is: class-ece474@engr.orst.edu This name is case sensitive.
Questions, suggestions?.... Mail to:
traylor@ece.orst.edu