ECE 474/574 - VLSI System Design
CRN 30398/30451

Spring 2003

Instructor:
Roger Traylor
Office: 238 ECE Bldg.
E-mail:traylor@ece.orst.edu
Office Hours: Tu, Th 3:00 - 4:00 or by appointment

When and Where:
Tuesday, Thursday 8:00-9:20 AM; Kidder 364

TA:
Peroly Natesan
E-mail: natesan@engr.orst.edu
Office Hours: M 2-4, Th 6-8

Text
"The Students Guide to VHDL" by Peter Ashenden.

Prerequisites
The stated prerequisites are ECE 375 and ECE323. In reality, proficiency with UNIX, really good with digital logic design, especially state machines and data paths. Having taken ECE471 is a plus.

Class Description
This class focuses on system-level design and implementation of Very Large Scale Integrated (VLSI) devices, specifically, ASICs and FPGAs. The emphasis is on system-level as opposed to circuit-level issues.

Overall Class Objective
Each student should be able to translate a high-level design specification into a working digital system using contemporary tools and techniques. To do this each student will be able to:

• properly write a design specification for a non-trivial digital system.
• competetly describe a hierarchical digial design using the synthesizible subset of VHDL.
• correctly partition a large design using top-down design techniques.
• use HDL simulation tools to quickly trace down errors (bugs).
• competetly use a programming editor such as vi or emacs.
• write a reasonable set of synthesis constraints.
• backannotate timing into a structural VHDL design to check timing.
• write a do-file for stimulus for a digital design.
• consturct a testbench for validating a HDL design.
• write reasonable place and route constraints for a Xilinx FPGA.
• describe the effects and methods to avoid problems with such issues as simultaneous switching outputs, clock skew, high speed termination, power supply decoupling, and asynchronous interfaces.
• create digital designs that conform to generally accepted standards of robust digital design.

Once the specification is completed, you will describe the system in VHDL. This system is then simulated and modified until correct behavior is observed. The VHDL design is then synthesized into gates. The gate level design is then regressed against the VHDL description and checked for proper behavior and timing. After this, timing information is back annotated and regression is done again.

When your design is complete, you will submit your final revised specification. You will also electronically submit all your VHDL code. I will compile, synthesize, and resimulate your design against a set of published test vectors.

Essential VHDL Document

Essential VHDL pgs 0 - 23
Essential VHDL pgs 24 - 46
Essential VHDL pgs 47 - 60
Essential VHDL pgs 61 - 76
Essential VHDL pgs 77 - 106
Essential VHDL pgs 107 - 127

RMU Documents

CAD Tool Pages:

Lecture notes on Top Down Design.

ECE474 Design Teams

Testbenches for the project

Scripts for the project

You may work in groups on homework if you wish. Sharing of design approaches, philosophy, general block diagrams or coding ideas is strongly suggested. However, sharing between groups of detailed information such as detailed block diagrams, state machine diagrams, or actual VHDL code is not approved and will meet with the strongest action that I can bring.

Getting Class information

Students who register early for ECE474/574 are automatically added to the class mail list. You may not be on the list at first if you register late. You should be added within a day or so. The name of the class list for ECE474/574 is: class-ece474@engr.orst.edu This name is case sensitive. Mail on the class list is archived at:
www.engr.orst.edu/classes/ece/ece474/archive

Grading

ECE474 Grades
ECE574 Grades

ECE 474 Schedule and Assignments

Questions, suggestions?.... Mail to: