HTML> ECE 474

ECE 474 - VLSI System Design
CRN 30379

Spring 2004

When and Where:
Tuesday, Thursday 8:00-9:20 AM; Kidder 364

Instructor:
Roger Traylor
Office: 238 ECE Bldg.
E-mail:traylor@ece.SPAM.edu (replace "SPAM" with "orst")
Office Hours: Th 3:00 - 4:00 or by appointment

TA:
Martin Held
E-mail: held@ece.SPAM.edu (replace "SPAM" with "orst")
Office: 211 Dearborn Hall, office #10 (Look for the Ghost in the Shell poster)
Office Hours: Tu, Th, 1:30-2:30

Text
"VHDL Programming by Example", 4th Ed. by Douglas Perry.

Prerequisites
The stated prerequisites are ECE 375 and ECE323. In reality, you will need proficiency with:

UNIX, shell scripting or PERL
really good digital logic design skills
state machine design

Class Description
This class focuses on system-level design and implementation of Very Large Scale Integrated (VLSI) devices, specifically, ASICs and FPGAs. The emphasis is on system-level as opposed to circuit-level issues.

Overall Class Objective
Each student should be able to translate a high-level design specification into a working digital system using contemporary tools and techniques. To do this each student will be able to:

properly write a design specifiaton for a non-trivial digital system.
competetly describe a hierarchical digial design using the synthesizible subset of VHDL.
correctly partition a large design using top-down design techniques.
use HDL simulation tools to quickly trace down errors (bugs).
competetly use a programming editor such as vi or emacs.
write a resonable set of synthesis constraints.
backannotate timing into a structural VHDL design to check timing.
write a do-file for stimuluous for a digital design.
consturct a testbench for validating a HDL design.
describe the effects and methods to avoid problems with such issues as simulteneous switching outputs, clock skew, high speed termination, power supply decoupling, and asynchronous interfaces.
create digital designs that conform to generally accepted standards of robust digital design.

The Project
The centerpiece of this class is a large design project. It will be executed much as it would be in an industrial setting. As such, timeliness, neatness, and clarity are important. The project is presented as a precise written description of how the system should work. This will involve writing specifications for the modules and the system (chip level) that will implement the system. The specification will include all block diagrams, interfaces, state machines, and data paths.

As modules are specified, you will describe them in VHDL. The modules and/or system is then simulated and modified until correct behavior is observed. The VHDL design is then synthesized into gates. The gate level design is then regressed against the VHDL description and checked for proper behavior and timing.

We will then do a full scan insertion to implement a testable chip. Resimulation will then be done again to verify that correct functionality is still present. A quick timing check will be made to verify nothing has been broken.

After the entire, scan inserted system has been verified for correct opeation, a silicon place and route will be done and paracitics extracted and once again, backannotated to the original vhdl design and verified with full timing information from the place and route.

When your design is complete, you will submit your final revised specification. You will also electronically submit all your VHDL code. I will compile, synthesize, and resimulate your design against a set of published test vectors.

You may work in groups on homework and the projects if you wish. Sharing of design approaches, philosophy, block diagrams or coding ideas is strongly suggested. However, sharing of detailed information such as state machine diagrams, or actual VHDL code is not approved and will meet with the strongest action that I can bring.

Grades

Grade Spreadsheet

Essential VHDL

Essential VHDL Part 1
Essential VHDL Part 2
Essential VHDL Part 3
Essential VHDL Part 4
Essential VHDL Part 5
Essential VHDL Part 6

Reading Assignments

X's in Simulation
Resets - how to use
SSO performance of TI logic
Understanding Ground Bounce

Project files and more

TAS VHDL Source Tarball
TAS Specification PDF
Risc Core v2.0.2 Specification Document
Risc Core v2.0.3 Specification Document
Risc Core v2.0.4 Specification Document
Risc Core v2.0.5 Specification Document
Risc Core v2.0.6 Specification Document
SPASM Revision 1, Originally by Matthew Ballance. (Install into ~/bin)
SPASM Revision 2, Originally by Matthew Ballance. (Install into ~/bin)
SPASM Manual v1.3
SPASM Manual v1.4 Updated to include blt, bs, shr instructions, and a few other minor fixes
ram.vhd For use in testbenching
risctest.s Basic Assembly code for testing the risc processor
risc_core2_0 revision 1 Blackboxed design for testbenching
risc_core2_0 revision 2 Blackboxed design for testbenching
Broken risc_core2_0 Broken Blackboxed design for testbenching and fun
synth_script Synthesis script skeleton
Debug Testbench from hw6

Homework

Homework will be posted here. All homeworks, unless otherwise noted, are due 8am in class.

Homework 1: TAS Deconstruction. Due Thursday, Apr. 8th.
Homework 2: Testbenching. Due Thursday, Apr. 15th.
Homework 3: ALU. Due Thursday, Apr. 22th.
Homework 4: Register File. Due Thursday, Apr. 29th.
Homework 5: RISC Specification. Due Monday, May. 10th by 5pm in Traylor's mailbox.
Homework 6: RISC Implementation. Due Monday, May. 17th, by web submission.
Homework 7: DFT Scan Chain Insertion. Due Midnight Friday, May. 28th, by web submission.
Homework 8: DFT Scan Chain Insertion. Due Midnight Sunday, June 6th, by web submission.

Getting Class information

A mail reflector (or group, list) for the class will be established by the beginning of class. This "mail group" is where you find information about important "stuff". The mailgroup is how I communicate with you outside the classroom. It can also be used as an interactive forum where you discuss problems and solutions. Such usage is encouraged.

Students who register early for ECE474/574 are automatically added to the class mail list. You may not be on the list at first if you register late. You should be added within a day or so. The name of the class list for ECE474/574 is: class-ece474@engr.orst.edu This name is case sensitive.

Grading

About 40% of your grade will come from the project. The rest will come from quizzes (~25%) and (~35%) from lab/homework. I reserve the right of to change final percentages depending upon the difficulty of the project and labs.

Lecture Notes in pdf Format

Mar 30 - Top Down Design
Apr 1 - Modeling with Top Down Design
May 6 - Metastability
May 11 - Synthesis
May 13 Tesign for Test
May 18 Partical scan
May 18 - Iddq testing
May 20 Verification of large designs
May 20 Verification cont'd
May 25 - IC packaging
May 26 - Simultaneous Switching Outputs
June 1 - VLSI Clock Distribution

Questions, suggestions?.... Mail to:

traylor@ece.orst.edu

ECE 474 - VLSI System Design CRN 30379