When and Where:
Tu,Tr 8:30-9:50 am; KEAR 212 (old Apperson Hall)
Instructor:
Roger Traylor
Office: 3095 Kelley Engineering Center
E-mail: traylor@ece.NOSPAM.edu (replace "NOSPAM" with "orst")
Office Hours: Tu 4:00 - 5:00pm, Wed 3:30 - 5:30pm or by appointment
TA:
Ming Hung Kuo
E-mail: kuom@engr.NOSPAM.edu (replace "NOSPAM" with "orst")
Office: TBA
Office Hours: Wed 1-3pm, Kelley Lab
Text:(not manditory)
Essential VHDL
RTL Synthesis Done Right
By Sundar Rajan
(self-published)
Class Objective:
At the completion of this class, each student should be able to:
You may work in groups on homework and projects if you wish. Sharing of design approaches, philosophy, block diagrams or coding ideas is strongly suggested. However, sharing of detailed information such as state machine diagrams, or actual VHDL code is not approved and will meet with the strongest action that I can bring.
A mail reflector (or group, list) for the class will be established by the beginning of class. The mailgroup is how I communicate with you outside the classroom. It can also be used as an interactive forum where you discuss problems and solutions. Such usage is encouraged.
Students who register early for ECE474/574 are automatically added to the class mail list. You will be added to the list later if you register late. If auditing, I will have to manually add you to the list. In either case, you should be added to the list within a day or so.
The name of the class list for ECE474/574 is: ece474-sp09@engr.NOSPAM.edu This name is case sensitive. You know what to put in place of "NOSPAM"
Running graphical CAD programs on Windows:
Download: (get font package installers too)
SSH Secure Shell and
Xming
Once installed,
-start the X server
-start SSH
-create a new profile to access one of the ENGR servers
(be sure to tell SSH to tunnel X11 connections... How to do this)
-start the connection.
-type in "xterm" to specify an X terminal session
-invoke whatever program you want.
Running graphical CAD programs on Mac OSX:
Install X11 from Mac install CD if not already installed.
From the prompt in the X11 or Terminal window: ssh -Y -l [username] [machine]
Invoke whatever program you want.
Running graphical CAD programs on Linux:
Install SSH if its not installed already.
From the command prompt: ssh -Y -l [username] [machine]
Invoke whatever program you want.
If your are running a Mac, Bash is the native OS X shell. Just open a terminal or X11 window and you are all set. Likewise, most Linux distros use the Bash shell as their native shell.
1) Using only the course text book, you complete a homework set.
References: None
2) You work with a group to complete a homework set.
References: I worked concurrently with Joe Smith, and Sam Brown on this
homework set as part of a study group.
3) You are stuck on how to draw a timing diagram on a homework set
and ask Joe Blow how he approached the problem.
References: Joe Blow explained how to set up the timing diagram
on problem 1.
4) You cannot get your simulation to give correct results. You look
at Sally's working code.
References: I looked at Sally's code to try and figure out what
was going wrong.
Grade Spreadsheet
HW2 Comments
HW4 Comments
HW7 Comments
Week | Date | Subject | Design Work | Supplemental Readingoptional reading in green |
|---|---|---|---|---|
| 1 | 3/31, 4/2 | What's this class about?(.pdf)
(.ppt) Intro to ASICs(.ppt) ASIC Design Basics(.pdf) (.ppt) -Top-down and Bottom-up Design -Architecture and Paritioning -Practical limitations Intro to HDL Design VHDL: what is it? -origins, motivation Weekly project discussion |
Exercises with Hierarchy and Design HW 1: Blocks and Gates Due Thursday, April 9, in class tas.vhd fifo.vhd TAS Requirements Document(.pdf) |
Rajan: Chapt 1,2(just get basic understanding) Rajan: Chapt 9 (p167-176) Cramming more components onto ICs (The original paper on Moore's Law written in 1965) Good Designers Must Fail (more risk, more learning) Truthful Schedules? (Lies, damn lies, and engineering schedules) Hierarchical Design (Pros and Myths about hierarchical design) Drawing Block Diagrams |
| 2 | 4/7, 4/9 | Scripting for EDA tools(.pdf)
(.ppt) Bash Shell doit1 doit2 doit3 averager.vhd do.do clean PERL Testbenches Design Management Weekly project discussion |
HW 2: Scripts and Testbenches HW2 tarball Submitting help Spec for Multiplier Due Friday, April 17, to TEACH website by 11:30pm |
Writing Shell Scripts Bash Programming Introduction Advanced Bash Programming Beginners Introduction to Perl Perl FAQ Scripting for IC Flows |
| 3 | 4/14, 4/16 |
ENTITY, ARCHITECTURE, PORT -the basics of VHDL Compenent Instantiation -structural design, lables, -positional and named association GENERIC Clause Text I/O Data Types and Operators Data types Package std_logic_1164 Operators, overloading Signal Assignment Signal Assignment Busses mux2_1_4wide.vhd mux4_1_4wide.vhd modelsim.tcl Conditional Signal Assignment incomplete specifications Selected Signal Assignment use of OTHERS making choices with "|" Weekly project discussion |
HW 3: Combo VHDL circuits .synopsys_dc.setup Due Fri, April 24, in ECE or my office by 5:00pm |
Rajan: Chapt 2 (reread) Rajan: Chapt 3, pgs 27-31 (Concurrent assignments) Rajan: Chapt 11, pgs 222-225 (Generics) Rajan: Chapt 14, pgs 291-303 (text i/o) |
| 4 | 4/21, 4/23 | Concurrency PROCESS statement Sequential operators and Variables IF and relational operators CASE statement and OTHERS LOOP statement Delays in VHDL Attributes Synthesis Intro TCL for DC Weekly project discussion |
HW 4: Synthesis scripting with Combo Logic Synthesis TCL script "dc_syn" .synopsys_dc.setup Due Fri, May 1, to TEACH web site by 11:30pm |
Rajan: Chapt 3, (gates, decoders, encoders) Rajan: Chapt 11, (loops, attributes, varaibles, generate) Rajan: Chapt 3, pgs 141-155 (delay types, ) Partitioning for Synthesis |
| 5 | 4/28, 4/30 |
Inferring Storage Elements State Machines in VHDL -Coding syles -Enumerated States -Glitchless State Machines Mealy Outputs Sync vs Async Reset Inclass Exercise - What am I? Answers Weekly project discussion |
HW 5: State element synthesis Waveforms for HW5 Due Fri, May 8, in my office or the ECE office |
Rajan: Chapt 5 (Registers and Latches) Synchronous vs Asynchronous Resets (Which type of reset should I use?) X's in Digital Simulation (When "X" is your friend) Rajan: Chapt 6 (Finite State Machines) Opencores coding guidelines Coding guidelines (lite) |
| 6 | 5/5, 5/7 |
Interactive Classwork Session -TAS data paths -TAS state machines |
HW 6: HDL State Machines Due Wed, Feb 20, in class Simulation dofiles: TBD dofiles in tarball golden_results |
|
| 7 | 5/12, 5/14 | Midterm (Monday, 7pm, location to be announced) Timing and area constraints Timing Constraints Problems and Questions -Latches -Combinatorial loops -Failure to run at speed -SDF errors Debugging Pointers Timing Verification -Static and Dynamic -Multicycle paths -False paths Static Timing/ Reports Weekly project discussion |
HW 7: Sequential Logic Synthesis Full submittal Due Wed, Feb 27, to TEACH web site by midnight list dofile Skeleton synthesis script | |
| 8 | 5/19, 5/21 | Metastability Design for Test -Fault test vs. verification -Finding and propagating faults -Ad hoc, partial scan, full scan -Test vectors -DFT-aware design Partial Scan Iddq Testing Problems caused by DFT Fixing Hold Violations Weekly project discussion |
HW 8: scan insertion Due Wed, Mar 5, in class or my office by 5pm, electronic part by midnight implement_scan script schematic - noscan schematic - scan ready |
|
| 9 | 5/26, 5/28 |
Equivalency Checking - part 1 Equivalency Checking - part 2 Discussion of Final Project |
Final Project: Factorial Geneator Factorial Geneator work description Perl script to fix dft directory issues TCL for dc_shell to implement scan Bash script to run fast scan Testbench for factorial |
|
| 10 | 6/2, 6/4 | (3/10)Discussion of Final Project (3/12)Eric Campbell - Mentor Graphics (3/15)Class eval/recap -Snacks provided |
Questions, suggestions?.... Mail to:
traylor@ece.SPAM.edu (replace SPAM with orst)
