ECE 474/574 - VLSI System Design
CRN 53471/53472 - Spring 2017

  M,W,F 1:00PM-1:50PM; KEC 1001

  Roger Traylor
  Office: KEC3095
  Office Hours: Wednesday, 3:00PM-5:00PM

  Gurjeet Singh
  E-mail: singhg@oregonstate.NOSPAM
  Office: Kelley atrium
  Office hours: Tu 3-5pm

  Jain Sanket
  E-mail: jainsa@oregonstate.NOSPAM
  Office: Kelley atrium
  Office hours: Th 3-5pm

Schedule and Assignments

Week Dates Topics Homework
1 Apr 3,5,7 Architecture and Partitioning
Inclass Accumulator Design (sturcture)
Architecture and Partitioning (cont.)
Inclass Accumulator Design (control and timing)
Digital Design Methodology
Design Review - 32-bit Multiplier
Inclass 32-bit Multiplier Design
Finish 32-bit multiplier timing and control design
2 Apr 10,12,14 About HDLs
Verilog modules, ports, instantiation
Verilog always blocks
Verilog Execution Semantics
if/else, unique, priority
case, unique, priority
Top level Verilog of 32-bit multiplier
.synopsys_dc.setup file
design vision script file file
instructions to help synthesize
3 Apr 17,19,21 Assign Statement
The if...else Statement
The case Statement
initial Block
Vim System Verilog setup
Using Vsim part 1
Using Vsim part 2
4 Apr 24,26,28 Synchronous Logic
Synchronous Logic Blocks
Moore-type State Machines
system verilog workflow
One-Hot State Machines
Mealy State Machines
Finish code and simulation of 32-bit multiplier
Homework 2
Due Wednesday next week(May,3,2017)
In Class quiz Friday May 28th,2017
5 May 1, 3,5 Homework 3 due wednesday(May 10th 2017)
6 May 8,10,12 Homework 4 (due Wednesday May 17)
7 May 15,17,19 Inclass design : TBD
Homework 5 (due wednesday May 24)
8 May 22,24,26 Inclass design : TBD
Homework 6 due(Wednesday May 31)
9 May 29,31,June 1 Homework 7 due Finals week
10 June 5, 7, 9