ECE 626 WINTER 2004
- Lectures: MWF 12:00--12:50pm, in Owen 106
- Lecturer: Gabor C. Temes, Professor, 203 Owen Hall, temes@ece.orst.edu
- Office Hours: MW 1-2 pm or by appointment
- Text Book : “Analog Integrated Circuit
Design”,
D. Johns and K. Martin,Wiley, 1997
- Teaching Assistant: Kingsuk
Brahma, 208 Dearborn Hall, brahma@ece.orst.edu
- Office Hours: W 3-5 pm only
Syllabus
Announcements
Midterm Solutions are Up
Lecture Notes
Introduction
Sample&Holds
(Chap 8, J&M)
Switched
Capacitor Circuits
(Chap 10 J&M)
Ladder
Filters
Scaling
of SCF’s
Sampled Data System
Direct
Charge Tranfer
Non-Ideal
Effects
Gm-C/Continuous
Time Filters
(Chap 15 J&M)
Basics of Data Converters (Chap
11 J&M)
Digital to Analog Converters (Chap
12 J&M)
Analog to Digital Converters (Chap
13 J&M)
Oversampled Data Converters (Chap
14 J&M)
TESTS
Homeworks
Pseudo HW #1 has been assigned
Pseudo HW #2 has been assigned
Pseudo HW #3 has been assigned
Homework Solutions
Project
Mini Project #1
Design the circuits, and
simulate the time-domain performances, of the
T/H stages shown in Figs. 8.4 - 8.9 of the text. Use the transistor
parameters on p. 370, and assume Lmin = 0.5 um. The
circuits need to
sample input signals of frequencies up to 15 MHz, and the clock sign
alternates between 0 V and 5 V, with a 100 MHz frequency and a
rise/fall time of 1 ns. You may use a transistor-level design or a
one-pole macromodel with
limited slew rate for the
opamps, and realize
the buffer as an opamp in a unity-gain feedback configuration. Aim for
an overall 9-bit performance;
don't overdesign any component.
If you are just going to use the
single pole slew limited macromodel for the opamp then you should definitely be
using the parameters on page 370 for the transistors acting as switches. If you
are however going to implement a complete transistor level design for the
entire circuit including the opamps/buffers you are encouraged to use advanced
models like .5u or .35u or .25u processes.
A possible implementation for a
macromodel of an opamp is a VCCS with an output resistor and capacitor and the
slew limitation can be modeled as
For Vin<=Vmax Iout=Gm*Vin
For Vin>Vmax Iout=Gm*Vmax*(the sign of Vin; whether its positive or negative)
Use either HSpice or Spectre(Cadence)