When and Where:
Monday, Wednesday 10:00-11:20 am; WGND 106
Instructor:
Roger Traylor
Office: 3095 Kelley Engineering Center
E-mail: traylor@ece.NOSPAM.edu (replace "NOSPAM" with "orst")
Office Hours: Wed 4:00 - 5:00pm or by appointment
TA:
Timothy Reinholt
E-mail: reinholt@ece.SPAM.edu (replace "SPAM" with "orst")
Office: Batcheller 349
Office Hours: Tuesday/Thursday, 3-4 pm; (bring warm clothes)
Text:(not manditory)
Essential VHDL
RTL Synthesis Done Right
By Sundar Rajan
(self-published)
Class Objective:
At the completion of this class, each student should be able to:
You may work in groups on homework and projects if you wish. Sharing of design approaches, philosophy, block diagrams or coding ideas is strongly suggested. However, sharing of detailed information such as state machine diagrams, or actual VHDL code is not approved and will meet with the strongest action that I can bring.
A mail reflector (or group, list) for the class will be established by the beginning of class. This "mail group" is where you find information about important "stuff". The mailgroup is how I communicate with you outside the classroom. It can also be used as an interactive forum where you discuss problems and solutions. Such usage is encouraged.
Students who register early for ECE474/574 are automatically added to the class mail list. You will be added to the list later if you register late. If auditing, I will have to manually add you to the list. In either case, you should be added to the list within a day or so.
The name of the class list for ECE474/574 is: ece474-w06@engr.NOSPAM.edu This name is case sensitive. You know what to put in place of "NOSPAM"
1) Using only the course text book, you complete a homework set.
References: None
2) You work with a group to complete a homework set.
References: I worked concurrently with Joe Smith, and Sam Brown on this
homework set as part of a study group.
3) You are stuck on how to draw a timing diagram on a homework set
and ask Joe Blow how he approached the problem.
References: Joe Blow explained how to set up the timing diagram
on problem 1.
4) You cannot get your simulation to give correct results. You look
at Sally's working code.
References: I looked at Sally's code to try and figure out what
was going wrong.
Grade Spreadsheet
HW3 grades and comments
Period | Date | Subject | Design Work | Reading | |
|---|---|---|---|---|---|
| 1 | Monday, Jan 9 | Introduction to ECE474/574 Design Creation top down design (TDD) modeling, simulation |
Hierarchy Exercise HW 1: Block Diagram Reconstruction Due Friday, Jan 13, in TA's mailbox by 5pm TAS sourcecode tarball Latest TAS sourcecode tarball TAS Requirements Document |
Rajan: Chapt 1,2 Rajan: Chapt 9 (Design Partitioning) Rajan: Chapt 11, pgs 222-225 (Generics in Scalable and Parameterizable Design) Moore's Law* (The original paper on Moore's Law written in 1965) No Exponential is Forever, but We Can Delay Forever? (Gordon Moore at ISSCC 2003 on extending Moore's Law) Micorprocessors circa 2000 (A look at difficulties in building advanced chips) |
|
| 2 | Wednesday, Jan 11 | Inclass Pretest Models and Simulation block diagrams naming, rules for blocks, files busses state machine descriptions Intro to HDL Design VHDL: what is it? origins, motivation for using it |
Good Designers Must Fail (more risk, more learning) Truthful Schedules? (Lies, damn lies, and engineering schedules) |
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| - | Monday, Jan 16 | MLK Day - University Closed |
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| 3 | Wednesday, Jan 18 |
ENTITY, ARCHITECTURE, PORT the basics of VHDL Compenent Instantiation structural design, lables, positional and named association lists GENERIC Clause Scripting for IC Flows IC Design Flow - Part 1 |
Rajan: Chapt 14, pgs 291-303 (text i/o) Hierarchical Design (Pros and Myths about hierarchical design) Bash Programming Introduction Advanced Bash Programming Intro to Perl NCSA PERL Tutorial Nicely Formatted PERL man pages |
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| 4 | Monday, Jan 23 | Data Types and Operators Data types Package std_logic_1164 and others Operators and overloading Signal Assignment Signal Assignment Busses and describing them Quiz #1 |
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| 5 | Wednesday, Jan 25 | Concurrency Conditional Concurrent Signal Assignment incomplete specifications Selected Concurrent Signal Assignment use of OTHERS making choices with "|" Generate statement Generate and I/O Shells?? TAS 50Mhz state machines and timing |
FIR Filter Modeling HW 2: Perl model of FIR Filter Filter coefficient file Due: In class Wed, Feb 1 |
Rajan: Chapt 3, (gates, decoders, encoders) Rajan: Chapt 11, (loops, attributes, varaibles, generate) Example design spec 1 Example design spec 2 |
|
| 6 | Monday, Jan 30 | ASSERT statement PROCESS statement Sequential operators and Variables IF and relational operators CASE statement and OTHERS LOOP statement Delays in VHDL Attributes Quiz #2 |
Rajan: Chapt 3, pgs 141-155 (delay types, ) |
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| 7 | Wednesday, Feb 1 | Inferring Storage Elements State Machines in VHDL Coding syles Enumerated States Glitchless State Machines |
HW 3: Multiplier Testbench Creation HW 3: mult testbench skeleton code HW 3: "doit" script HW 3: Behavorial multiplier |
Rajan: Chapt 5 (Registers and Latches) Synchronous vs Asynchronous Resets (Which type of reset should I use?) X's in Digital Simulation (When "X" is your friend) | |
| 8 | Monday, Feb 6 | State Machines (continued) Mealy Outputs Opencores coding guidelines Coding guidelines (lite) IC Design Flow - where are we? Quiz #3 |
Rajan: Chapt 6 (Finite State Machines) Example VHDL structures Counter w/sync and async reset DRAM Model 8-bit, 4 location dual-port FIFO 2:1 Mux 16-bit register 8 location, 16-bit register file 8-bit shift register Dual Rank Synchronizer 8-bit reg with tri-state output Even or Odd Parity Generator |
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| 9 | Wednesday, Feb 8 | Metastability Where and when it occurs -Concequences -Characterization -Solutions Sync vs Async Reset Synthesis Intro Partitioning for Synthesis |
First cut of your spec due in class Trade specs with each other |
TBA | |
| 10 | Monday, Feb 13 | Basics of Synthesis Logic Synthesis II Delay calculations -Global and local delay -Setup and hold slack -Clock skew Synthesis scripts -Synthesis constrains Feature size scaling isses |
Return redlined spec to owner. |
How to grade a spec adder.vhd control.vhd multi_reg.vhd mult_rtl.vhd simple multiplier (.pdf) See the follow sections: Chapt. 3 "The Art of VHDL Synthesis" -Registers, Latches, Resets -State Machines -Arithmetic and Relational Logic -Multiplexors and Selectors |
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| 11 | Wednesday, Feb 15 | ASIC design flow, second blush Design for Test Fault test vs. verification Finding and propagating faults Ad hoc, partial scan, full scan Test vectors Design for test Partial Scan Iddq Testing |
Scan ATPG process guide Review Chapt. 2 |
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| 12 | Monday, Feb 20 | Project Discussion TCL for DC Timing and area constraints Problems and Questions -latches -combinatorial loops -failure to run at speed -sdf errors Debugging Pointers Quiz #4 |
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| 13 | Wednesday, Feb 22 |
Timing Constraints Fixing Hold Violations Static Timing/ Reports Timing Verification -Static and Dynamic -Multicycle paths -False paths |
HW 4: RTL Coding HW 4: Multiplier RTL Coding Due: Midnight, March 3 via web submission |
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| 14 | Monday, Feb 27 |
Equivalency Checking - part 1 Equivalency Checking - part 2 Design for Test Fault test vs. verification Finding and propagating faults Ad hoc, partial scan, full scan Test vectors Design for test Partial Scan Iddq Testing |
Functional Verification |
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| 15 | Wednesday, Mar 1 | VLSI Clock Distribution Clock networks PLL and DLL operation and usage |
Cooling Embedded Designs (Overview of cooling methods and tools) |
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| 16 | Monday, Mar 6 | ASIC design flow, third blush VLSI Clock Distribution Clock networks PLL and DLL operation and usage Clockless or Self-timed logic |
HW 5: Constraint files, Synthesis, Optimization HW 5: Multiplier Logic Synthesis Due: Midnight, Mar 10 via web submission .synopsys_dc.setup file Skeleton dc_shell synopsys tcl script |
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| 17 | Wednesday, Mar 8 | ASIC design flow, the big picture IC Packaging Packaging families Environmental issues Thermal issues Electrical issues |
HW 6: Scan insertion, test vector generation Due: Midnight, Mar 17 via web submission |
Understanding and Minimizing Ground Bounce (Fairchild Semi. App. Note) SSO Performance of TI Logic Devices (TI App. Note) Data Coding for Low Noise (Encoding method for lessening SSO noise) |
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| 18 | Monday, Mar 13 | Simultaneous Switching Outputs (SSOs) SSO Origins SSO Manifestations SSO problem Mitigation Buffer strength Graduated turn-on buffers High Fidelity signaling Measuring Rd(on) of buffers Termination of T-lines ?? |
SSO Simulation Terminating a T-line |
Ten Commandments of Excellent Design (Still good advice) | |
| 19 | Wednesday, Mar 15 | Final Exam (given out in class) Due tuesday of finals week, March 21 at 1800 Class recap Donuts and Coffee |
TBA |
Questions, suggestions?.... Mail to:
traylor@ece.SPAM.edu (replace SPAM with orst)